In the design of very high performance integrated circuits, designers have to deal with the distribution of clock frequencies in the GHz domain. There are several prior art design strategies to distribute GHz clock signals to their destinations. In one strategy, to which the teachings of this invention apply, the clock signal is distributed through a global clock distribution network to reach all the surface area of the chip, using a two-stage distribution network. This global distribution is preferred because most of the synchronous devices in the design work at such frequencies and are placed throughout the surface area of the chip.